1. Field of Invention
Invention relates to integrated circuit design, particularly to hierarchical layout display system and methodology for amoeba-type component perimeter placement.
2. Description of Background Art
Electronic circuit and system designs are becoming increasingly complex, sometimes having over ten million transistors. To handle such complex magnitude, circuit designs may be represented hierarchically. Furthermore, computer-aided design (CAD) tools facilitate definition and verification of logic-level, as well as physical-level design representations. Additionally, floor-planning and placement steps serve to convert design representation from logical to physical.
Floor-planning usually provides "high-level" block (i.e., rectangular) diagram representing hierarchical logic design, wherein such blocks may represent top or child-level components in design hierarchy. Moreover, automated placement tools may use floor-planning to provide "strict" or "loose" suggestion of preferred preliminary placement of sub-logic components within blocks. With strict floor-planning approach, components in each floor-plan block are generally placed in confines bordering correspondingly drawn block, whereas in loose floor-planning approach, automated placement algorithm generally has more freedom for components to lie beyond boundaries drawn in given hierarchy.
Oftentimes, however, design trade-offs arise, for instance, whereupon strictly enforced floor-planning results in undesirable longer wire connection lengths, which translate to physically larger and/or un-route-able layouts as compared to more loosely governed floor-plans. Hence, more strictly enforced floor-planning approach generally require unduly tedious effort to achieve desired physical design. But, such strictly enforced floor-planning may nonetheless offer designers better control, for example, over design timing, as well as more independent implementation of hierarchical sub-components. Furthermore, in comparison to such strict approach, relatively loose floor-planning, as well as so-called "flat" (i.e., non-hierarchical) automatic placement approaches tend to place components in generally non-hierarchy manner and shape, whereby resulting constraints may generate more route-able placements.
In view of various design tradeoffs, therefore, there is increased need to provide improved automated methodology and system to assist electronic design engineers to accomplish higher quality hierarchical circuit and system designs without unreasonable burden, particularly in terms of time, effort, and difficulty of use.